Featured image above: Synopsys Chair and CEO Aart de Geus. Synopsys
Artificial Intelligence (AI) is permeating and adding value at every junction of life and commerce. Semiconductors are a vital piece of the AI value chain, accelerating ML workloads, including foundational models like generative AI. But did you know that companies like Synopsys, whose technology is used to design chips, are themselves now using advanced AI; in effect, using AI to optimally design AI?
Synopsys recently held its Synopsys Users Group (SNUG) event in Silicon Valley, bringing together innovators, engineers and industry leaders to discuss the latest developments in chip design and electronic design automation (EDA). Echoing what’s going on in most of the tech world, the theme was leveraging AI into chip design and EDA. Synopsys Chair and CEO Aart de Geus delivered the keynote speech, highlighting the importance of AI, how it is transforming the tech landscape and the role of Synopsys.ai in revolutionizing the EDA suite.Synopsys.ai in revolutionizing the EDA suite.
Although I was unable to attend SNUG in person, I could feel de Geus’s energy and passion for Synopsys.ai while I attended the event digitally. I believe he communicated well the innovative implications of AI within chip design and EDA, and as someone who has been connected to the chip industry for more than two decades, I am just as excited.
The mind-boggling complexity of chip design
Chip design has become increasingly complex, and chip engineers are facing unprecedented challenges that arise from the increasing demand for the most advanced silicon chips. As transistors become smaller and design densities increase, AI has emerged as a powerful solution to enhance engineering productivity and silicon quality.
To put it into perspective, chip design teams face a staggering number of possibilities when designing, verifying and testing the advanced chips at the latest process technologies. These teams aim to find the best-case scenario for power, performance and area (PPA), considering the billions of transistors that are all tightly packed into one die. To address this, Synopsys has introduced the first full-stack AI-driven EDA suite, Synopsys.ai, which increases design productivity, improves design quality, reduces design costs and boosts design efficiency.
AI-driven EDA design suite
Synopsys.ai encompasses three main components: DSO.ai for improving PPA, VSO.ai for faster and better verification coverage and TSO.ai for improving test coverage with fewer patterns. testing. These solutions offer engineers significant productivity and performance improvements by tackling repetitive tasks and allowing experts to focus on value-added tasks.
de Geus summarized the design process very well: capturing the existing IP data leads to modeling it, which in turn leads to simulating, analyzing, optimizing and automating it, then finally reusing the IP created from completing all these tasks. While this has already been the process for reusing IP without AI, it is now also the same process for implementing AI into the workflow of EDA and chip design. Reinforcement learning models use large collections of existing IP and chip design data to train and automate this process.
DSO.ai (Design Space Optimization AI) was the first AI application in EDA, and Synopsys has seen strong momentum in its adoption, including its first 100 production tapeouts. A tapeout is a term used to refer to the final result of the design process for integrated and printed circuits before being sent to manufacturing. This tapeout milestone is significant because it shows the real-world advantages of AI in the design implementation of new chips.
It also shows the power of the reinforcement learning approach. If chip designers aim to get the best PPA result, reinforcement learning is the ultimate tool for seeking optimal designs. It is like using an AI engine to make the best moves in chess, but at a much higher degree of complexity.
VSO.ai (Verification Space Optimization AI) uses AI to speed up verification of designs. Verification ensures the correctness and reliability of each chip design. If different areas of the design are not checked for functionality, reliability and even viability, the chip will be prone to bugs and, in many cases, will not work as intended. Checking for functionality and completeness in the verification process is called coverage closure, and it is a crucial step in ensuring that the digital design has been thoroughly tested and validated.
The challenge for verification is that it takes a long time to verify a design that has billions of coverage areas. It is a tedious and complex task, especially when layers and layers of IP are being used. Using AI in the verification process saves time by improving overall verification efficiency and by enabling verification engineers to find bugs quicker and identify areas of improvement within the design.
There is also a lot of room to improve the verification process using AI. AI could intelligently explore the design space and suggest optimal configurations or trade-offs within the design. It could learn from previous designs and develop targeted recommendations. I am impressed with the implementation of AI in the verification process and only see it getting better from here on out. It should significantly impact the entire electronic design lifecycle and play a critical role in reducing the overall time to market for chip designs.
TSO.ai (Test Space Optimization AI) addresses the testing process for a chip design after it has been manufactured to ensure functionality and quality. While the digital design of the chip can be changed more easily, the manufactured chip requires a different process for handling defects. Engineers use automatic test pattern generation (ATPG) and design-for-testability to create more efficient test patterns. The challenge within the testing process is optimizing how effectively the test patterns can identify potential defects in the chip while balancing the run time and cost of these tests. TSO.ai reduces the run time and costs by automating the test program generation for enhanced defect coverage, fewer test patterns and faster time to results.
Synopsys continues to expand its offering to include AI-driven analog, manufacturing, mask synthesis and signoff solutions, solidifying its position as the leading provider of AI-driven EDA tools.
Synopsys is undoubtedly one of the leaders at the forefront of revolutionizing chip design through its innovative AI-driven EDA suite. The company’s investment in AI technology has already yielded significant improvements in productivity and performance, positioning Synopsys as a leader in the industry.
The integration of AI across the entire EDA suite, including implementation, verification and testing, should significantly advance chips’ capabilities. It is an exciting time for EDA and the broader industry. With AI-driven EDA tools, engineers can focus on more innovative tasks, deliver smarter, safer and more secure chips, and continue to innovate in the ever-evolving tech landscape.
As the industry continues to evolve, Synopsys.ai will play an increasingly vital role in shaping the future of chip design. The success of Synopsys.ai, as demonstrated by the impressive results achieved in productivity and performance, serves as a testament to the transformative power of AI for EDA. The tech community can eagerly anticipate the continued innovation and growth spurred by Synopsys’s investment in AI-driven EDA solutions.
Note: Moor Insights & Strategy co-op Jacob Freyman contributed to this article.