Cadence is well along an agentic path for its many tool suites. In February of this year, it announced the ChipStack AI Super Agent — which followed its acquisition of ChipStack in November 2025. Cadence built on that in May at its CadenceLIVE event, where I attended the launch of the company’s Super Agents for EDA. At the same time, Cadence announced an AgentStack to manage its many Super Agents, and it introduced a three-layer stack of agents, algorithms, and accelerated compute. (I covered all of this in detail in my CadenceLIVE 2026 write-up.)

Since then, Cadence has extended its strategy across two axes, going deeper by taking ChipStack to “Level 5” autonomy and wider by deploying AuraStack with agentic AI for PCB layout and advanced packaging. Together, these announcements help to make Cadence one of the few, if not the only, EDA vendor that can claim agentic AI coverage across the full electronics design flow, from silicon to system. Beyond that, both announcements deepen the company’s already established partnership with NVIDIA.

From Copilot to Colleague: ChipStack Reaches Level 5 Autonomy

At Computex 2026, Cadence announced that ChipStack had graduated to a Level 5 autonomous agent that the company was calling a “virtual agentic design engineer.” Cadence has been workshopping its naming scheme for AI agent autonomy levels for a while, using it as far back as CadenceLIVE 2025. The company has been building towards this capability and borrowing nomenclature from the automotive industry’s autonomous driving terminology, which I think works pretty well.

Achieving Level 5 status means that ChipStack is transitioning from step-by-step prompting to having the agent evaluate intermediate results, make decisions on next actions, and iterate to closure. It does this across spec understanding, RTL generation, verification planning, formal analysis, simulation, debug, and convergence. In concept, this allows engineers to shift from executing tasks to managing outcomes and then letting the agents focus on specific tasks. Cadence claims that ChipStack at Level 5 results in 40x faster RTL, compressing verification loops that might take five weeks into less than one day. This is something that NVIDIA CEO Jensen Huang specifically discussed at Cadence LIVE as he shared his vision for creating infinitely more virtual chip designers.

While I like the Level 5 branding, it is fairly aggressive, and the idea of “fully autonomous” may need more explanation, considering that engineers still need to inspect, guide, and collaborate with the ChipStack Super Agent.

Grounding and Governance: Trust Is Paramount

Cadence differentiates itself from other companies deploying AI agents by the engines and algorithms that its agents rely on for physics-based accuracy. Cadence isn’t coming into this as a company that wants to enter the EDA space using AI, but rather as an industry leader in EDA that is now using AI to help solve systems problems. The company already has tools in place to address many of the design problems that its customers have, but now it is using agentic AI to help solve these problems more quickly and with fewer inputs.

I also think it’s meaningful that Cadence is working closely with arguably the most important company in AI, NVIDIA, to leverage proven frameworks and models. Cadence’s agent execution solution is the NVIDIA OpenShell runtime, which NVIDIA has worked diligently to develop for its own agentic workloads. Cadence is also using NVIDIA’s Nemotron models with OpenShell for ChipStack’s AI Super Agent. NVIDIA is aggressively updating the Nemotron family of models, which includes Nano-, Super-, and Ultra-sized models. Partnering with NVIDIA to use OpenShell and Nemotron models is one way that Cadence reassures its semiconductor customers that using an AI Super Agent like ChipStack is safe and will protect their IP.

AuraStack: Completing the Silicon-to-System Story

AuraStack is Cadence’s new AI Super Agent built on Allegro AI Studio, which Cadence claims is the world’s first agentic AI platform for PCB and advanced packaging design. Cadence says that AuraStack enables faster time-to-market, especially thanks to a 15x improvement in productivity. AuraStack uses the same architecture as ChipStack, but applied to system design. This covers many phases of design, including planning, constraints, physical structure definition, IP reuse, place and router, DFM, and unified closed-loop multiphysics. AuraStack also represents Cadence’s extension of its AI Super Agents beyond chip design into related areas of design. Cadence now claims to have the only end-to-end agentic EDA stack for semiconductor makers. In support of this claim, Cadence’s acquisition of Hexagon in early 2026 further bolstered its range of tools for system design and analysis (SDA).

At the launch event, Cadence referenced some customer experiences with AuraStack, including the automotive electronics supplier Forvia Hella, which said it reduced the placement of 300 components from four days to four minutes. TSMC said it was able to perform 3DFabric substrate auto-routing at 100x productivity. NVIDIA said it leveraged the Cadence Millennium M2000 to accelerate multiphysics by 20x with AuraStack. The ability to enable multiphysics co-optimization earlier in the design process reduces the need for later-stage re-spins, which are much more costly and time-consuming.

Cadence and NVIDIA Continue to Grow in Tandem

The EDA company and the chip maker have a symbiotic relationship, in which they are customers of each other as well as co-development partners. In the end, this close relationship is about accelerating the pace of innovation with AI, whether that’s by using NVIDIA’s Blackwell chips or Cadence’s Millennium M2000 design supercomputer.

While we’ve seen this partnership go on for years now, from my perspective it only grows in relevance and scope with every new year. While Cadence is an important supplier for NVIDIA, it also serves as a showcase for what NVIDIA’s chips can do. Besides already accelerating its agentic AI story with NVIDIA’s GPUs, Cadence also has many CPU-based tools that may eventually be GPU-accelerated.

Cadence’s Execution Is Methodical — and Crucial for the Industry

It’s worth it to review the timing of what Cadence has done in the past year. Its ability to complete the ChipStack acquisition in November 2025 and then launch the first related product in February 2026 was already impressive. After that, the company announced its Super Agent portfolio in April 2026, moved to Level 5 autonomy by May, and introduced system-level capabilities by July. That is admirably methodical for a company working on such science- and engineering-intensive products. In doing this, Cadence is also methodically executing on its strategy of using AI to uplevel from assistance to autonomy in silicon and from silicon to system-level design. All of this is consistent with the 10-year arc that Cadence laid out in 2025, which outlined the company’s shift from AI to physical AI to scientific AI.

Cadence says that it is giving early access to Level 5 autonomy in the second half of 2026, and there will be some time to evaluate Cadence’s claims for AuraStack’s acceleration then as well. It will also be interesting to see the competitive responses from Synopsys and Siemens, and how customers receive the autonomous agents that touch production silicon. Cadence is ultimately trying to help customers like NVIDIA solve the engineering bottleneck that Huang spoke about at CadenceLIVE 2026, and its recent announcements appear to reflect meaningful progress in enabling both virtual and human engineers to get more done.