At AMD’s datacenter and AI day, the company announced several datacenter products as it works to further increase its performance leadership across a range of workloads—including cloud, artificial intelligence (AI) and technical computing. I’ll break down the cloud and technical computing announcements in the following few sections. And for the AI-related announcements, check out Moor Insights & Strategy CEO and principal analyst Pat Moorhead’s coverage here.

First some context

Before getting into what was announced, let’s set the stage to better appreciate what AMD has delivered. In the six years since AMD launched the first of its new generation server processor (codenamed Naples), the x86 market has been shaken up considerably. First, Intel, the once near–monopolistic player, had some execution setbacks, allowing a competitive AMD to expand its growing footprint among cloud service providers (CSPs).

As AMD began to increase its share of the x86 server market, AWS deployed its own homegrown server CPU based on Arm architecture. Not only did AWS deploy this processor, called Graviton—it deployed at scale. This was a seminal moment for Arm as it demonstrated that the architecture could deliver value in a market filled with many skeptics. As Graviton became popular, Ampere launched its own Arm-based server CPU, called Altra). Today, every major CSP is deploying Arm-based instances at scale, serving the needs of customers running containerized cloud-native workloads that thrive on scalable architectures.

Why would the CSPs care about deploying Arm in the datacenter? Doesn’t it add complexity to datacenter operations? The answer: It’s all about compute density. While these Arm chips lose most of their low-power advantage when juiced up and packaged for servers, you can still stuff a lot of CPU cores into a single server. This proved true with both Ampere and Graviton. Getting more cores in a server means I can get more computational power per rack unit, which in turn means I can get more customers on a server, thus bringing down my operational cost. Think about it, if a CSP acquires a server with 128 cores at a discounted rate and then rents out each one of those cores to customers—there’s a lot of money to be had. And if I can reduce the cost of my servers, the per-core ROI gets better and better.

This is why Arm is so attractive to CSPs, and it’s why both AMD and Intel see Arm as a serious competitive threat. It’s not only because Arm is taking market share today, but also because—just like Intel unseating “big iron” in the early 90s—nothing is keeping Arm from working its way up the performance stack and stealing more and more share from the x86 players. It could even be easier for Arm, given that its architecture has shown strong performance numbers relative to x86.

Bergamo — AMD’s cloud chip

Bergamo is AMD’s response to Arm. This CPU ships with a core density and power efficiency that rivals Arm

AMD packed a lot into Bergamo, shrinking the core size (relative to Genoa, the standard 4th Gen AMD EPYC CPU) by 34%. This allows AMD to pack each of its eight compute complexes with 16 cores (versus eight cores in Genoa). The result is a CPU optimized for performance per watt instead of per core.

These impressive numbers make sense when we consider that “Bergamo” is packing a core/thread density ratio that’s 2.1 times higher than Xeon. I would have liked to have seen AMD show a detailed performance comparison to Ampere at its event, with hyperthreading turned on and off. Arm architected its Neoverse processor (which Ampere Altra is built on) specifically as a single-threaded architecture for optimal cloud performance. As a result, CSPs have no choice in how they deploy Ampere-based platforms. Will a hyperthreaded x86 part—such as the AMD or Intel cloud CPUs coming later this year—deliver a performance-per-watt mark that Ampere can’t hit?

With the above said, I like what AMD has done with Bergamo. This is as much about the company’s posture toward competitive threats in the market as it is about the product itself. The AMD of a few years ago would not have responded so strongly.

Genoa-X — 3D V-Cache enablement for technical computing

EPYC’s performance leadership has driven strong adoption in both cloud and high-performance computing (HPC). In the enterprise, EPYC has also found success in what we could call commercial HPC: technical computing. What is technical computing? Think product design and performance simulation—the high-performance workloads that engineers, scientists and others use that require a lot of horsepower to handle big datasets. These workloads benefit from high-performing cores accompanied by large chunks of cache. And this is where AMD’s 3D V-Cache comes into play.

Because die sizes are physically limited, packing more cache onto the core complex becomes extremely difficult. So, instead of building out, AMD designed up (hence 3D). This not only allows for more cache but enables better-performing cache. And the result is dominance from a workload performance perspective.

If you are looking at the above chart and saying, “No fair—EPYC has way more cores,” rest assured that AMD’s performance leadership is still impressive even when coming down the stack.

Again, I like what AMD is doing. While the company has had less success in the enterprise than in cloud and HPC, it is appealing to the enterprise use cases that share the performance requirements of the supercomputer clusters that make up the HPC Top 500 list. This continued push may allow AMD to land and expand in that stubborn market segment.

Final Thoughts

It was a good day for AMD. The company continues to execute an aggressive plan to drive continued performance leadership in the datacenter. A move that the AMD of a few years back would not have made. And Bergamo is an excellent response to a competitor that can’t be taken lightly.

I am looking forward to seeing how Bergamo compares to Ampere from a performance-per-watt and performance-per-dollar perspective. And ultimately, I’m curious to see the CSP adoption of AMD’s cloud CPU. My gut tells me TSMCis going to be busy.