Intel Updates IDM 2.0 Strategy With New Node Naming And Transistor And Packaging Technologies

Intel’s new node naming INTEL

Back in March, Intel CEO Pat Gelsinger rolled out the company’s “IDM 2.0” strategy. You can find my write-up here. Net-net, the company announced two new fabs, seriously re-entered the foundry business with IFS, and provided more details on its technologies and partner-based manufacturing (TSMC, GF, Samsung) and partner-based technology approach with IBM. You can also find more information on IDM 2.0 here when I interviewed Pat Gelsinger in June. 

Today, the company provided a few updates on its technologies and announced a new node-naming schema.  

New naming schema

Intel’s first big announcement of the day is its new node naming schema for its next few generations of semiconductor technology. Intel recognizes that its naming schema requires a change to represent semiconductor technology better and I like the approach.

From my vantage point, the semiconductor industry recognizes that the naming schema behind nodes is already flawed. The problem is that the press, some analysts, and even some OEMs haven’t internalized this. A “7nm” chip from one competitor may be consistent with another “5nm” chip, or a “5nm” chip may have most transistor lengths considerably longer than “5nm”. Samsung and TSMC admit this inconsistency, and Intel is finally doing something about it by changing its naming schema away from the “nm” naming and closer to what TSMC and Samsung are doing. I think it is smart to move away from the measurement naming schema because, in the process, it will refocus innovation of the semiconductor, and I am hoping it will make comparisons easier. I’m hopeful we’ll move away from “smaller meaning faster” is innovation, which isn’t necessarily the case, and toward “efficiency and density,” including packaging more defines innovation.

Industry Recognizes Node Naming Inconsistency INTEL

Moving forward, Intel’s naming schema for its 10nm SuperFin will stay the same, and the following nodes will do away with the “nm” name. The Enhanced SuperFin will be called “Intel 7”, and what was previously known as the “7 nm” will be referred to as the “Intel 4”, followed by the “Intel 3”. The Intel 7 boasts a 10-15% perf/watt gain with FinFET transistor optimizations and is currently in volume production. The Intel 4 should have a 20% perf/watt gain and take advantage of EUV lithography. The Intel 3 should have Power and area improvements over the Intel 4. 

The Intel 3 node will complete that era of semiconductors, and Intel will move into the “Angstrom era” of semiconductors with a completely different naming schema. The angstrom is the next lower measurement after the nanometer (nm). One angstrom is a tenth of a nm, so 2 nm would be 20 angstroms. Intel’s next node will be called Intel 20A, with the “A” signifying the era of angstrom semiconductors and 20 being about where Intel would consider the node’s measurement to be. I say “would consider” because, in all reality, you cannot measure the dimensions of a transistor, and this has been true for over a decade. Intel is saying that the classification of this transistor would fall into the 2nm category according to “industry standards.” In saying this, I don’t believe Intel is being disingenuous or inconsistent with its naming schema, rather creating a resetting point in time as if it were at 2nm or 20 angstroms. I have no problem with this new naming schema because it does two things: it brings its naming schema toward an industry standard and dissipates confusion with partners, customers, and competitors. Although the 20 angstroms would be an accurate placement in terms of Intel being at the 2nm mark if it were to keep its legacy naming schema, it does not represent the dimensions of its node, and the 20 is almost arbitrary. The focus is more on the “A” for angstrom and how it is an era, not a measurement. In its video, Intel says 18A is already in development for 2025.

PowerVia and RibbonFET

Semiconductor innovation is more than having the shortest transistor length, as discussed above. Being on the bleeding edge of semiconductor innovation is also about having a higher density chip in other ways. Higher density incorporates two main factors: smaller nodes, the industry focus, and advancing packaging technology. When we look to the future of semiconductor innovation, what will be the more common innovating factor of the two will be more efficient packaging. 

Transistor Innovations: PowerVia and RibbonFET INTEL

In the “Angstrom era,” the Intel 20A will feature two groundbreaking technologies—a new transistor architecture named RibbonFET and new power delivery innovation called PowerVia. RibbonFET is Intel’s first new transistor architecture since FinFET about a decade ago. RibbonFET is a type of GAA (gate all around) architecture called nanoribbons, where the gate is wrapped around the channel. This architecture enables higher drive current at all voltages resulting in higher performance. PowerVia brings power in from the backside so that more resources are available for optimizing signal routing. Intel says the overall result is a performance boost at the IP block level and reduced power leakage. By bringing power from the backside, RibbonFET and PowerVia can both be put on the same piece of silicon. The combination of these two is coming with Intel 20A.

Next-generation of Foveros

Intel’s roadmap furthers its Foveros technology that improves the packaging of semiconductors. Foveros is Intel’s 3D packaging technology that leverages wafer-level packaging technology. Meteor Lake, which will include Intel 4, is the second generation to include Foveros. Foveros Omni and Foveros Direct are Intel’s next generation of Foveros technology with advanced interconnects. Intel says Foveros Omni provides die-to-die interconnect and modular designs that allow for die disaggregation, mixing multiple top die tiles with multiple base tiles across fab nodes. In other words, Foveros Omni allows for the base die to be smaller than the die that is stacked above it, eliminating the TSP overhead and allowing lower costs.

Foveros Direct eliminates the need for solder in the silicon, creating a direct copper-to-copper bonding for low-resistance interconnects. Intel says it enables sub-10-micron bump pitches that open new concepts for functional die portioning, previously deemed unachievable.

Packaging Innovations: Foveros Omni and Foveros Direct INTEL

In closing

Semiconductor innovation is all about delivering a targeted level of performance for a targeted workload assessed across power, performance, cost, and time-to-market. This has been true for the over 30 years I have been in tech. The way we go there has changed over time, though. 

Technically, Moore’s Law did slow down, meaning that we couldn’t rely on a doubling of transistors in the same area every two years. The industry has responded with more accelerated computing (GPU/ASIC/FPGA), putting most of the burden on the programmers. It also is responding with new ways of increasing transistor density which is still very important and novel packaging.

I’m glad to see Intel move from nm-bound node naming and adopt a schema more like TSMC and Samsung. I’m even happier to see more transistor and packaging innovations that give me more confidence in Intel’s future.  Intel has been very forthright with its roadmap with transparency I haven’t seen for a while, which should give its customers and investors higher confidence in its future. I believe the Amazon (packaging) and Qualcomm (20A) announcements added a tremendous boost to IFS story.

Note: Moor Insights & Strategy co-op Jacob Freyman contributed to this article.