For quite some time now, many chip industry watchers have questioned the future sustainability of Moore’s Law. Named after Intel founder Gordon Moore, this industry constant observes that semiconductor densities double every 2 years, and has underpinned the industry for 52 years. Recently, some have also begun to question whether Intel has lost its vaunted technology and manufacturing leadership as its fabrication competitors, Taiwan Semiconductor(TSMC) and Samsung Electronics , ready their new 10nm generation products for production in the same time window as Intel, planned for 2H 2017. Intel decided to set the record straight by hosting a 5-hour marathon deep dive on its Technology and Manufacturing Group (TMG), and it left little doubt that both concerns are vastly overstated. In addition to sharing data that equated its 14nm products, which have been shipping for 3 years now, to its competitors’ upcoming 10nm products, Intel made several important technology announcements that further demonstrate the company’s innovation and leadership.
Intel’s New Math: 14 = 10 (so 10 = 7, right?)
Intel took several hours to articulate its position that the company has not lost its advantage, and that Moore’s Law is alive and well. Put simply it presented evidence that Intel’s innovations in its existing 14nm manufacturing process yield chips with densities that rival what it expects from its competitors’ upcoming 10nm process. Intel then showed how its 10nm process, available later this year, will maintain this 3 year advantage. Which means, it contends, that its 10nm process will rival its competitors’ 7nm process in the subsequent generation. Note that Intel’s arguments are based on a density metric measuring the density of transistors in 2 specific logic blocks, a simple NAND gate and a complex flip flop. Some would argue that this approach does not adequately characterize a chip’s performance, power and density characteristics, but it seems to me like a reasonable proxy.
So, what makes Intel’s 14nm better than that of TSMC or Samsung’s 16nm FinFET (also used by Globalfoundries )? First, Intel has developed a set of “Hyper Scaling” technologies unique to Intel that account for its superior PPA (Performance, Power, Area) attributes (more on that later). Intel also points to a lithography technology called Self Aligned Dual Patterning, in part to explain why its 14nm equals others’ 10nm, and to the follow-on Self Aligned Quad Patterning to sustain its ability to better scale its 10nm parts.
While one needs to be cautious that Intel cannot know with certainty what its competitors are or are not doing when it draws these conclusions, its argument is fairly compelling. The figure below shows how Intel stacks up in terms of logic density over time, projecting the future 10nm densities based on what Intel would have achieved without its special sauce described above.
Intel’s projection of competitor’s 10nm densities in red compared to Intel’s existing 14nm products in blue.
Intel went on to describe a portfolio of technologies that it is baking into its 10nm products. The figure below details these hyper scaling innovations, which when combined produce a 2.7 fold improvement in transistor density.
Intel’s 10nm Hyper Scaling technologies. (Source: Intel)
The figure below shows how Intel 10nm compares with its prior process nodes, as well as where Intel believes its competitors’ 10nm parts will land. The punch line here is that Intel projects that it will maintain a 2x leadership in transistor density in its 10nm products vs. the competition. Basically, Intel is saying that the competition does not have comparable technology with its 10nm hyper scaling. But Intel will need to keep up its blistering pace of innovation, or these advantages are likely to be temporary; recall how the competition copied Intel’s 3D FinFET (Fin Field Effect Transistor) advantage in just one generation.
Intel’s projected logic transistor densities in blue would yield a 2x advantage over its unnamed competitors
So, when you net it all out, Moore’s Law seems to be safe, at least for the next couple generations. Once again, there is more to performance and power than just density and resulting die area, so we will all have to await actual 10nm production silicon from the four remaining advanced process fabs—Intel, TSMC, Samsung and Globalfoundries (which uses Samsung’s technology)—to validate these projections.
Intel Announces New Process and Packaging Technologies
Intel announced a couple of major new technologies at the event. The first is an update to its 22nm technology and manufacturing process called 22FFL to significantly reduce power consumption. Here, Intel added FinFET technology to produce parts that will offer a 100x reduction in total transistor power leakage, targeting mobile and IOT applications for power-restricted environments. However, note that Globalfoundries has taken the early lead here two years ago with its 22FDX FD-SOI process for low power mobile devices, believing that the FD-SOI approach is superior to FinFET for mixed digital and RF applications. In fact, Global has already engaged over 50 customers in mobile, IoT and automotive projects.
Intel claims that its new 22FFL process reduces transistor leakage by 100 fold. (Source: Intel)
Finally, Intel talked about its approach to interconnect chips using silicon embedded in the substrate of the multi-chip package instead of the slower interposer technology typically used today. With a name only a geek could love, the “EMIB” (Embedded Multi-Die Interconnect Bridge) can interconnect chips manufactured on different process nodes, without the through-silicon vias and backside interposers, which could be a boon for lowering costs, increasing performance and lowering latencies (the trifecta for chips). It turns out that advanced process nodes such as 10nm FinFET is great for performance hungry cells such as processor cores but is overkill for things like I/O and communication. Intel is already using EMIB in its upcoming Stratix10, which combines a Xeon processor and a 16nm Altera FPGA on the same package. One could imagine a wide range of applications, including interconnecting CPUs and GPUs, or tying together a Xeon with the future Nervana Engine for AI. This would be a significantly faster solution than the typical PCIe interconnect used today for accelerators, which only delivers 15GB/s Intel said it is realizing 600GB/s bandwidth through the Stratix10 EMIB connection, which is roughly 6 times the throughput of other approaches.
Intel’s EMIB embeds silicon interconnects directly into the substrate, eliminating the traditional interposer
The Technology and Manufacturing day’s intent was not just to explain why Intel chips would be superior products. The company wanted to make it very clear why Intel should be the preferred foundry for chip designs demanding advanced process node manufacturing, and it told a very convincing story. Intel showed that it has not lost its lead in advanced process technologies, and that it can sustain Moore’s Law progression for the foreseeable future. And while EMIB is not new, it is another reason Intel hopes that it can lead as a custom foundry for the industry’s fabless chip companies’ business. As the world continues to digitize everything we interact with, Intel’s competitors increasingly become TSMC and Samsung, not just other chip companies. And based on the information shared at this event, Intel looks to be in excellent position going forward.