I will be honest with you. For years, I didn't quite understand all the attention that the RISC-V ecosystem or the solutions were getting. I saw very small CPU cores being used without high level operating systems in self-contained environments. These were replacing Arm M0 solutions in hard drive controllers. There is value in that, but it's just not the type of thing that I think changes the game in the industry.
Also, from a business model point of view, you still had to pay somebody to design the RISC-V chip, so what was the point, you’ll either pay the designer or Arm? There are no free lunches. The other thing that was a tad boring was that I didn't see solutions with a lot of compute power or RAS features that would make a difference in the data center market. Hard drive controller type of CPU performance. Yes, I did recognize the ISA extensibility to accelerators, but it appeared Arm plugged that hole and that it could cause ISA “compatibility” issues down the line.
Then Ventana Systems came onto the scene.
Over the past six months, the company shared with me some of the details of its plans that seemed quite compelling. This week at the RISC-V Summit the company officially announced what had been in stealth for years- Veyron, what the company calls “the world’s first datacenter-class RISC-V CPU.” It gave details on Veyron V1 and showed that a year later we would see a V2.
This is more than slideware. I believe the company has major design commitments spanning the datacenter to the edge that could be in operational systems in late 2023.
So, what capabilities does the Veyron V1 CPU chiplet, processor, or the IP have?
- Eight wide, aggressive out-of-order instruction pipeline
- 5nm process technology
- 16 cores per cluster
- High core count multi-cluster scalability (up to 192 cores)
- 48MB of shared L3 cache
- Advanced side channel attack mitigations
- IOMMU & Advanced Interrupt Architecture (AIA)
- Full RVA22 application profile compliance
- System level code profiling
What strikes me about this bullet list is that it’s built for high-performance, RAS (Reliability, Serviceability. Availability) and security. Higher levels of RAS and security are required in the datacenter, the datacenter edge, carrier use cases, and in the software-defined vehicle.
The company is committing the highest single thread and socket performance versus other RISC-V designs. From what I gather, this will be, at first, an easy bar to cross. No one else, to my knowledge, is this far. The performance bar in the next two years are with Arm and X86 ISAs and Ventana wasn’t shy about showing it outperformed current processors like Xeon Ice Lake, EPYC Milan (Zen 3), and AWS Graviton 3 with ones it will have in late 2023.
Easy math says that Ventana would need to boost its future performance with V2 to beat the upcoming chips and IP from Arm, Intel, AMD, and AWS home-grown, but that may be missing the point. Ventana doesn’t have to beat everyone, it just needs to be in the respectable range, which, if the company delivers, it will. We can’t forget that the magic of a RISC-V based CPU isn’t just performance, it’s the custom instructions and accelerators that can be used.
While I had earlier dismissed the “extensible ISA” capabilities inherent in the RISC-V architecture as messy and replicable by Arm, the Ventana design wins all include this. The company has built around it a mesh of partners with solutions for storage, AI, 5G acceleration, and more. What I have to do more research on are the cross-software compatibility degree when we get many different flavors of RISC-V CPUs into the market.
Also interesting is that Ventana is targeting the same places early Arm-based implementations targeted and had success with. These are workloads like web hosting, in-memory databases, storage, load balancing, caching, CDN and streaming. This comes straight from the Arm playbook because…. it works, and many Ventana employees came from Arm-based datacenter processor companies. None of this should be a surprise.
Let’s talk software. This one is a tricky one. If there’s a question I hear most about the RISC-V degree of success in higher-order use cases, it’s software. I get it. We all watched the 10+ years it took to create the Arm stack for the datacenter. I am not ready to declare “success” or “finished” on this. Here is what I do know:
- Arm blazed the trail for non-x86 tools, firmware, BIOS, OS, and the most popular use cases with open-source software
- Cloud giants own their own software stacks and have the resources to move mountains
- those people learned the ins and outs of non-X86 and appear to more quickly take those skill sets to RISC-V with the leadership of Ventana
- logic says the time to RISC-V will be shorter than time to Arm
In the end, I will be most convinced by real companies running real production workloads. I think Ventana knows exactly what it’s getting into as it was front and center in the Arm software battle.
I previously didn’t see RISC-V as a viable alternative in data-centric environments as I witnessed the pain Arm and its partners went through and didn’t see enough differentiation for people to switch. Enter Ventana.
I can’t question design wins, though, and I believe Ventana has many. The reason they want to use Ventana are:
- enough performance today and confidence in future performance
- extensible ISA acceleration capabilities
- experienced leadership that has been through the x86 and Arm crucible
- go-to-market flexibility with IP, core and full processor
Both Ventana founders Balaji Baktha and Greg Favor have been through the fire before with the x86 and Arm wars. I believe the two have very few blind spots about what the company needs to do to get a foothold. If there’s any team that I think can do it in the RISC-V space, I believe it’s this one. Baktha and Favor can’t change the degree of competitive response, but the company can flawlessly execute on what looks like a good plan. I cannot wait for what the future holds for Veyron 1 and 2.