Cadence Touts Its Crucial Role For Chip Makers At Cadence LIVE 2024

By Anshel Sag, Patrick Moorhead - June 14, 2024
Cadence CEO Anirudh Devgan delivers the Cadence LIVE Keynote
Anshel Sag

Semiconductors are becoming even more complicated as their makers use chiplets, die stacking and new architectures to adapt to the needs of the AI-powered world. In this context, chip equipment and design software companies such as Cadence that have a systems-oriented approach are gaining more relevance. At this year’s Cadence LIVE event in Santa Clara, California the company laid out its vision for the future, showing how its many different products can help solve challenging problems within the semiconductor industry and beyond, from designing and testing individual transistors to modeling physics simulations for airliners and Formula 1 race cars. Cadence calls this “chips-to-system intelligent design acceleration”; its Cadence.AI platform seeks to address these needs by combining foundational LLMs with generative AI optimizations for problems of all sizes.

Dynamic Duo III

Dynamic duos—from Batman and Robin to Chewbacca and Han Solo—should complement one another so that the whole is greater than the sum of the parts. Cadence’s is no different. The company refers to the pairing of its two accelerated computing solutions for chip design and validation as its Dynamic Duo. These are two separate rack-mounted solutions, the Palladium Z3 and Protium X3, which Cadence designed to be the best at debugging hardware before its design is complete and then debugging the software that runs on that hardware before it’s manufactured.

Cadence CEO Anirudh Devgan talks about Cadence Dynamic Duo III
Anshel Sag

The Palladium Z3 uses an in-house Z3 emulation processor to allow engineers to emulate a chip design and verify that it works before sending it to the foundry for manufacturing. Once the Palladium Z3 is done with a design, it can transfer it to the Protium X3 for software debugging. Cadence says that Palladium Z3 and Protium X3 have unified compile and virtual/physical interfaces, which enable a three to five times faster bringing-up of the new design in software. The Protium X3 platform was built on AMD’s VP1902 adaptive SOCs, some of the most powerful FPGAs on the market. Together, these two products are scalable to 48 billion gates and deliver two times more emulation scale than the Palladium Z2 and three times more software debugging scale than the Protium X2. Both also offer 50% higher performance than the previous generation, leading to faster development cycles and cost savings on engineering hours.

Nvidia’s CEO, Jen-Hsun Huang, spoke highly of Palladium, stating that Nvidia has the largest installation of Palladium anywhere. He said this while on stage with Cadence’s CEO, Anirudh Devgan, during a fireside chat. During that conversation, Huang also said that Nvidia’s new Blackwell architecture would not be possible without Palladium, and that his company is “enamored” with Palladium. Considering that Blackwell is the most performant, complex and expensive GPU that Nvidia has created to date, it is exceptionally high praise that Huang would speak so highly of another company’s role in creating it. That said, Nvidia’s Bluefield DPU and Quantum Infiniband are also used as interconnects within Cadence’s Dynamic Duo III, so Huang also has a vested interest in Cadence’s success.

The Millennium M1

Nvidia’s GPUs also power Cadence’s new Millennium M1, which was announced in February 2024. The Millenium M1 is a computational fluid dynamics supercomputer that utilizes tightly coupled hardware and software acceleration. This supercomputer can help solve engineering problems in aerospace, automotive manufacturing and energy production that require calculating large eddy simulations. Cadence uses its own Fidelity LES Solver for these simulations. While Cadence doesn’t specify which Nvidia GPUs are inside the Millennium M1, companies including McLaren Racing and Honda already use the Millennium M1 for automotive racing and design. Cadence claims that Millennium M1 represents a 10x increase in throughput compared to CPU-only solutions, as well as a 17x reduction in power.

Cadence’s AI-Enhanced Design Tools

In addition to what I like to call its big-iron hardware solutions, Cadence has many software tools to empower chip designers during the various phases of development and production. Cadence also enhances many of its EDA, SDA, environmental and molecular-science tools with AI. This means that its Cerebrus, Virtuoso, Verisium, Optimality and Allegro X tools now have AI-driven features to make them more effective and powerful for users.

Cerebrus is Cadence’s tool for digital semiconductor design. The company says that its AI-driven automated approach to chip design delivers better power, performance and area while improving engineers’ productivity. Cadence calls this product its “intelligent chip explorer,” which utilizes generative AI to reinforce learning with LLMs to improve productivity. Cadence has also shared customer proof points from Broadcom, Canon, Microchip, Draper, Arm and GUC to validate its claims. During Cadence LIVE, the company also highlighted some of MediaTek’s successes from using Cerebrus, claiming that MediaTek achieved 5% smaller die area and a 6% reduction in total power.

Virtuoso Studio is Cadence’s suite of tools for analog and custom designs. It leverages AI to enhance workflows, although the company hasn’t shared many details on how that works. That said, at the event Cadence did validate Virtuoso Studio’s relevance by saying that it is used by 18 of the top 20 semiconductor firms and citing Samsung as a specific proof point. Cadence claimed that in migrating its analog IP from 14nm to 8nm, Samsung saw a 10x improvement in process migration thanks to Virtuoso Studio.

Cadence’s Verisium debug and verification suite, which uses AI for automation and analyses for digital chip verification, has two AI-enhanced design engines. At Cadence LIVE 2024, the company used Qualcomm as an example to discuss Verisium’s capabilities. It claimed that Qualcomm was able to reduce verification CPU hours on modem design by 20x, which is double Cadence’s claim that Verisium can improve verification productivity by 10x.

In addition to Verisium, Cadence also talked about Allegro X AI for PCB design, showing how North Atlantic saw a 10x faster PCB placement turnaround time with this tool. Cadence also touted its multi-physics system optimization platform Optimality; it claimed that customer Sanechips saw a 10x improvement in efficiency and 330% better return loss on its high-speed serializer/deserializer interface using Optimality.

With the industry continuing to move towards 3-D IC designs, Cadence also touted its Integrity 3D-IC platform, which incorporates many IP and design tools to improve final 3-D package designs. This means leveraging UCIe and other interface IP at Cadence’s disposal to maximize chiplet design efficiency and thermals.

Cadence also spoke about its involvement in the next generation of automotive intelligence, taking advantage of the many tools that it already deploys. One major customer that it used as a proof point for its automotive know-how was Tesla. While Cadence didn’t get Elon Musk to come on stage, the company did say that it was helping Tesla develop both the next-generation FSD computer for Tesla vehicles and the next-generation DOJO AI supercomputer, which will use multiple Cadence tools in its development.

Wrapping Up

While many people may not know what Cadence does, the company plays a critical role in enabling the semiconductor world we live in today—and the semiconductor world of the future. Within the industry, many know Cadence primarily as an EDA and verification tool provider, but as computational problems grow, so does the scope of what Cadence must do.

Cadence is becoming a systems solutions company, broadening the scope of the problems it solves. This reflects its recognition that the world is becoming increasingly complex and that systems approaches are the only way to solve the problems that arise from that level of complexity. Demand for semiconductor tools and system-level approaches will only increase as the world gets increasingly connected by semiconductors. With its AI-enhanced tools, Cadence is uniquely positioned to deliver those solutions.


Anshel Sag
VP & Principal Analyst | Website

Anshel Sag is Moor Insights & Strategy’s in-house millennial with over 15 years of experience in the IT industry. Anshel has had extensive experience working with consumers and enterprises while interfacing with both B2B and B2C relationships, gaining empathy and understanding of what users really want. Some of his earliest experience goes back as far as his childhood when he started PC gaming at the ripe of old age of 5 while building his first PC at 11 and learning his first programming languages at 13.

Patrick Moorhead

Patrick founded the firm based on his real-world world technology experiences with the understanding of what he wasn’t getting from analysts and consultants. Ten years later, Patrick is ranked #1 among technology industry analysts in terms of “power” (ARInsights)  in “press citations” (Apollo Research). Moorhead is a contributor at Forbes and frequently appears on CNBC. He is a broad-based analyst covering a wide variety of topics including the cloud, enterprise SaaS, collaboration, client computing, and semiconductors. He has 30 years of experience including 15 years of executive experience at high tech companies (NCR, AT&T, Compaq, now HP, and AMD) leading strategy, product management, product marketing, and corporate marketing, including three industry board appointments.