Over the years, the cost of designing a system on chip (SoC) has become significantly higher. Computers have transitioned from a homogenous architecture to a heterogenous computing architecture. Many variables in the past five years are attributed to the tripling in SoC cost, most notably the complexity and engineering that went into moving from 10nm to 5”nm”.
If we look at what it takes to design an SoC and its costs, it comes down to the costs of the CPU, architecture, physical IP, verification, and software development and testing. Cadence is one of the few companies in the technology industry with tools that customers use to build this IP and design SoCs. For those unfamiliar, these tools are called electronic design automation (EDA) CAD tools for SoCs.
SoCs have become increasingly complex, and the smaller and denser each design gets, the more EDA data is created. Each EDA design produces a lot of pieces that needs to be verified, and often this data is deleted to save space and resources for the next iteration of the design. Throughout the entire design process, the SoC design goes through various verifications to ensure there are no bugs and that the system works properly. As these systems have become more complex, verifying the design has taken up more time and resources. As the complexity rises, so do time and resources to verify a design.
The newly announced Verisium Verification platform and JedAI
Cadence has announced the Verisium AI-Driven Verification platform that uses AI from its Joint Enterprise Data and AI (JedAI) platform, which was also announced, to speed up verification workloads. Cadence says its Verisium AI-Driven Verification platform represents a generational shift from single-run, single-engine algorithms in EDA to algorithms that leverage big data and AI to optimize multiple runs and engines across an entire SoC design.
The innovative feature to focus on for the Verisium platform is that it accumulates data across the SoC design process and past projects. It then uses AI and ML models to optimize the design of the system.
- Verisium AutoTriage builds ML models for automating repetitive regression failures.
- Verisium SemanticDiff uses algorithms to compare source code and revisions of IP or SoC to pinpoint bugs hotspots.
- Verisium WaveMiner applies AI engines to analyze waveforms.
- Verisium Debug is a comprehensive debug solution that uses Cadence JedAI platform for AI-driven root cause analysis.
- Verisium Manager is Cadence’s full-flow IP and SoC-level verification management solution on the JedAI platform with AI-driven optimization.
Cadence has a more in-depth description of these apps, where I derived my simpler explanations. The Verisium manager works with the verification engines—Jasper, Xcelium, Palladium, Protium, and Helium—and brings them natively onto the JedAI platform.
Big data and AI analytics are driving the next generation of SoC design
One of the benefits of digitally transforming businesses is this exact principle—taking business data and turning it into valuable business analytics. On a macro scale, AI is using data from everywhere as a driver for efficiency, cost reduction, and effectively maximizing a business’ workload through analytics. Cadence has taken this big data and analytics principle and applied it to an SoC verification process, which should significantly improve the productivity and efficiency of the SoC design process.
SoC Verification is the second largest cost driver behind software because of the time and resources it takes to verify a design. The legacy method of SoC verification is also single-engine, single-run, and the sheer ability to perform multiple runs with multiple engines is incredible. Although it is a first-generation platform, I believe it should significantly reduce the amount of effort that goes into the verification process.
Since design data is also saved for future generations, as each SoC design becomes more complex, the Verisium and JedAI platforms should be equally as effective. It could even allow complex tasks within the design verification process to be simpler as each generation of these platforms become more comprehensive. AI-driven verification should lower the time to market and optimize a system’s power, performance, and area (PPA).
Another exciting effect of AI-driven SoC designs is that it could significantly make it harder for competitors like those in China to copy an SoC design. Since Industry standard design tools like Cadence’s EDA have become unavailable to those in China, copying these complex designs aided by AI would be increasingly difficult. AI could create a considerable rift between SoC designs here in the States and those in China, possibly reducing national security risks and copyright infringements.
The cost of an SoC has gone up considerably in the last five years, and one of the reasons is that the complexity of these systems has increased as SoCs have become smaller, denser, and more complex. Introducing AI analytics and big data into the verification process of SoC design could significantly reduce the time to market and allow system designers to pinpoint and optimize the PPA of a system.
Although this platform is the first generation from Cadence, I believe it should bring considerable improvement to the design of an SoC. This isn’t just my opinion. In the analyst deck, Cadence had supporting quotes from both Samsung and Mediatek.
Note: Moor Insights & Strategy co-op Jacob Freyman contributed to this article.